We know that a half adder circuit has one Ex – OR gate and one AND gate.įive NAND gates are required in order to design a half adder. Combining these two, the logical circuit to implement the combinational circuit of half adder is shown below.Īs we know that NAND and NOR are called universal gates as any logic system can be implemented using these two, the half adder circuit can also be implemented using them. If A and B are binary inputs to the half adder, then the logic function to calculate sum S is Ex – OR of A and B and logic function to calculate carry C is AND of A and B. The truth table and K Map simplification for carry is shown below. The truth table and K Map simplification for sum output is shown below. The same can be verified with help of Karnaugh Map. The sum output of the binary addition carried out above is similar to that of an Ex-OR operation while the carry output is similar to that of an AND operation. If we assume A and B as the two bits whose addition is to be performed, a truth table for half adder with A, B as inputs and Sum, Carry as outputs can be tabulated as follows. The block diagram of a half adder is shown below. Half adder is a combinational circuit that performs simple addition of two binary numbers. Some basic binary additions are shown below. Apart from addition, adders are also used in certain digital applications like table index calculation, address decoding etc.īinary addition is similar to that of decimal addition. out of these, binary addition is the most frequently performed task by most common adders. Adders can be constructed for most of the numerical representations like Binary Coded Decimal (BDC), Excess – 3, Gray code, Binary etc. Adders are a key component of arithmetic logic unit. Construction of half/ full adder using Ex-OR and NAND gates and verification of its operationĪdders are digital circuits that carry out addition of numbers.
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